Designing mobile radio frequency (RF) chips (e.g., mobile RF transceivers) is complicated by added circuit functions for support of communication enhancements. These mobile RF transceivers may be designed using semiconductor on insulator technology. Semiconductor on insulator (SOI) technology replaces conventional semiconductor (e.g., silicon) substrates (e.g., wafers) with a layered semiconductor-insulator-semiconductor substrate for reducing parasitic device capacitance and improving performance. In SOI devices, an active device is fabricated using an SOI layer, in which an SOI semiconductor substrate supports a buried oxide (BOX) layer as the insulator.
The active devices on the SOI layer may include complementary metal oxide semiconductor (CMOS) transistors. RF switch devices of mobile RF transceivers may be fabricated using CMOS transistors on SOI substrates. Unfortunately, successful fabrication of RF switch transistors using SOI technology is complicated by parasitic capacitance. For example, one criteria for rating the performance of an RF switch transistor is an off-state capacitance (Coff), in which the RF switch transistor is modeled as a capacitor during an off-state. The larger the off-state capacitance Coff, the larger the off-state leakage of the RF switch transistor and corresponding lower performance rating.
An RF switch may include a stack of RF switch transistors that are coupled in series for achieving a desired power handling capability, in which each transistor exhibits a predetermined breakdown voltage. Stacking of switch transistors for achieving the desired power handling capability (e.g., desired breakdown voltage) beneficially reduces the off-state capacitance Coff. Unfortunately, a desired breakdown voltage, as well as the off-state capacitance Coff scaling, begins saturating after a certain stack height, which may be due to parasitic capacitive coupling to the ground lines and/or the substrate. One technique for overcoming this problem is tuning the capacitance by increasing/decreasing (e.g., 10%-20%) the capacitance of each transistor in the stack, which leads to a uniform overall capacitance. A further increase in the capacitance is desirable for providing more uniform scaling.